/*
 * Copyright (C) 2018 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2018-09-04 11:00:16
 *
 */

#ifndef DMC_BIST_AUTO
#define DMC_BIST_AUTO

#define CTL_BASE_DMC_BIST_AUTO 0x61070000

#define REG_DMC_BIST_AUTO_BIST_CTRL_0           ( CTL_BASE_DMC_BIST_AUTO + 0x0000 )
#define REG_DMC_BIST_AUTO_BIST_CTRL_1           ( CTL_BASE_DMC_BIST_AUTO + 0x0004 )
#define REG_DMC_BIST_AUTO_BIST_CTRL_2           ( CTL_BASE_DMC_BIST_AUTO + 0x0008 )
#define REG_DMC_BIST_AUTO_BIST_CTRL_3           ( CTL_BASE_DMC_BIST_AUTO + 0x000C )
#define REG_DMC_BIST_AUTO_BIST_SIPI_DATA_0      ( CTL_BASE_DMC_BIST_AUTO + 0x0010 )
#define REG_DMC_BIST_AUTO_BIST_SIPI_DATA_1      ( CTL_BASE_DMC_BIST_AUTO + 0x0014 )
#define REG_DMC_BIST_AUTO_BIST_SIPI_DATA_2      ( CTL_BASE_DMC_BIST_AUTO + 0x0018 )
#define REG_DMC_BIST_AUTO_BIST_SIPI_DATA_3      ( CTL_BASE_DMC_BIST_AUTO + 0x001C )
#define REG_DMC_BIST_AUTO_BIST_SIPI_DATA_4      ( CTL_BASE_DMC_BIST_AUTO + 0x0020 )
#define REG_DMC_BIST_AUTO_BIST_SIPI_DATA_5      ( CTL_BASE_DMC_BIST_AUTO + 0x0024 )
#define REG_DMC_BIST_AUTO_BIST_SIPI_BIT_CTRL_0  ( CTL_BASE_DMC_BIST_AUTO + 0x0028 )
#define REG_DMC_BIST_AUTO_BIST_SIPI_BIT_CTRL_1  ( CTL_BASE_DMC_BIST_AUTO + 0x002C )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_0      ( CTL_BASE_DMC_BIST_AUTO + 0x0030 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_1      ( CTL_BASE_DMC_BIST_AUTO + 0x0034 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_2      ( CTL_BASE_DMC_BIST_AUTO + 0x0038 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_3      ( CTL_BASE_DMC_BIST_AUTO + 0x003C )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_4      ( CTL_BASE_DMC_BIST_AUTO + 0x0040 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_5      ( CTL_BASE_DMC_BIST_AUTO + 0x0044 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_6      ( CTL_BASE_DMC_BIST_AUTO + 0x0048 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_7      ( CTL_BASE_DMC_BIST_AUTO + 0x004C )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_8      ( CTL_BASE_DMC_BIST_AUTO + 0x0050 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_9      ( CTL_BASE_DMC_BIST_AUTO + 0x0054 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_10     ( CTL_BASE_DMC_BIST_AUTO + 0x0058 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_11     ( CTL_BASE_DMC_BIST_AUTO + 0x005C )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_12     ( CTL_BASE_DMC_BIST_AUTO + 0x0060 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_13     ( CTL_BASE_DMC_BIST_AUTO + 0x0064 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_14     ( CTL_BASE_DMC_BIST_AUTO + 0x0068 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_15     ( CTL_BASE_DMC_BIST_AUTO + 0x006C )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_16     ( CTL_BASE_DMC_BIST_AUTO + 0x0070 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_17     ( CTL_BASE_DMC_BIST_AUTO + 0x0074 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_18     ( CTL_BASE_DMC_BIST_AUTO + 0x0078 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_19     ( CTL_BASE_DMC_BIST_AUTO + 0x007C )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_20     ( CTL_BASE_DMC_BIST_AUTO + 0x0080 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_21     ( CTL_BASE_DMC_BIST_AUTO + 0x0084 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_22     ( CTL_BASE_DMC_BIST_AUTO + 0x0088 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_23     ( CTL_BASE_DMC_BIST_AUTO + 0x008C )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_24     ( CTL_BASE_DMC_BIST_AUTO + 0x0090 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_25     ( CTL_BASE_DMC_BIST_AUTO + 0x0094 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_26     ( CTL_BASE_DMC_BIST_AUTO + 0x0098 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_27     ( CTL_BASE_DMC_BIST_AUTO + 0x009C )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_28     ( CTL_BASE_DMC_BIST_AUTO + 0x00A0 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_29     ( CTL_BASE_DMC_BIST_AUTO + 0x00A4 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_30     ( CTL_BASE_DMC_BIST_AUTO + 0x00A8 )
#define REG_DMC_BIST_AUTO_BIST_USER_DATA_31     ( CTL_BASE_DMC_BIST_AUTO + 0x00AC )
#define REG_DMC_BIST_AUTO_BIST_RESULT           ( CTL_BASE_DMC_BIST_AUTO + 0x00B0 )
#define REG_DMC_BIST_AUTO_BIST_FAIL_ADDR        ( CTL_BASE_DMC_BIST_AUTO + 0x00B4 )
#define REG_DMC_BIST_AUTO_BIST_FAIL_DATA_0      ( CTL_BASE_DMC_BIST_AUTO + 0x00B8 )
#define REG_DMC_BIST_AUTO_BIST_FAIL_DATA_1      ( CTL_BASE_DMC_BIST_AUTO + 0x00BC )
#define REG_DMC_BIST_AUTO_BIST_FAIL_DATA_2      ( CTL_BASE_DMC_BIST_AUTO + 0x00C0 )
#define REG_DMC_BIST_AUTO_BIST_FAIL_DATA_3      ( CTL_BASE_DMC_BIST_AUTO + 0x00C4 )
#define REG_DMC_BIST_AUTO_BIST_LFSR_POLY        ( CTL_BASE_DMC_BIST_AUTO + 0x00C8 )
#define REG_DMC_BIST_AUTO_BIST_LFSR_SEED_0      ( CTL_BASE_DMC_BIST_AUTO + 0x00CC )
#define REG_DMC_BIST_AUTO_BIST_LFSR_SEED_1      ( CTL_BASE_DMC_BIST_AUTO + 0x00D0 )
#define REG_DMC_BIST_AUTO_BIST_LFSR_SEED_2      ( CTL_BASE_DMC_BIST_AUTO + 0x00D4 )
#define REG_DMC_BIST_AUTO_BIST_LFSR_SEED_3      ( CTL_BASE_DMC_BIST_AUTO + 0x00D8 )
#define REG_DMC_BIST_AUTO_BIST_MISS_CNT         ( CTL_BASE_DMC_BIST_AUTO + 0x00DC )
#define REG_DMC_BIST_AUTO_BIST_EXPT_DATA_0      ( CTL_BASE_DMC_BIST_AUTO + 0x00E0 )
#define REG_DMC_BIST_AUTO_BIST_EXPT_DATA_1      ( CTL_BASE_DMC_BIST_AUTO + 0x00E4 )
#define REG_DMC_BIST_AUTO_BIST_EXPT_DATA_2      ( CTL_BASE_DMC_BIST_AUTO + 0x00E8 )
#define REG_DMC_BIST_AUTO_BIST_EXPT_DATA_3      ( CTL_BASE_DMC_BIST_AUTO + 0x00EC )
#define REG_DMC_BIST_AUTO_BIST_XTK_MODE         ( CTL_BASE_DMC_BIST_AUTO + 0x00F0 )
#define REG_DMC_BIST_AUTO_BIST_FAIL_CNT         ( CTL_BASE_DMC_BIST_AUTO + 0x00F4 )

/* REG_DMC_BIST_AUTO_BIST_CTRL_0 */

#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_DATAWIDTH_MODE                       BIT(28)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_SIPI_AUTO_MODE                       BIT(27)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_SRAM_PORT_MODE                       BIT(26)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_READ_OUTSTANDING_EN             BIT(25)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_WRITE_OUTSTANDING_EN            BIT(24)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_CMD_DELAY(x)                    (((x) & 0x1FF) << 15)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_BW_TEST_MODE                    BIT(14)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_DATA_SIZE(x)                    (((x) & 0x7) << 11)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_BURST_LENGTH(x)                 (((x) & 0xF) << 7)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_DATA_PATTERN_MODE(x)            (((x) & 0x3) << 5)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_MODE(x)                         (((x) & 0x3) << 3)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_CLEAR                           BIT(2)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_START                           BIT(1)
#define BIT_DMC_BIST_AUTO_BIST_CTRL_0_BIST_ENABLE                          BIT(0)

/* REG_DMC_BIST_AUTO_BIST_CTRL_1 */

#define BIT_DMC_BIST_AUTO_BIST_CTRL_1_BIST_TRANS_NUM(x)                    (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_CTRL_2 */

#define BIT_DMC_BIST_AUTO_BIST_CTRL_2_BIST_START_ADDR(x)                   (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_CTRL_3 */

#define BIT_DMC_BIST_AUTO_BIST_CTRL_3_BIST_DATA_MASK(x)                    (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_SIPI_DATA_0 */

#define BIT_DMC_BIST_AUTO_BIST_SIPI_DATA_0_BIST_SIPI_DATA_00(x)            (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_SIPI_DATA_1 */

#define BIT_DMC_BIST_AUTO_BIST_SIPI_DATA_1_BIST_SIPI_DATA_01(x)            (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_SIPI_DATA_2 */

#define BIT_DMC_BIST_AUTO_BIST_SIPI_DATA_2_BIST_SIPI_DATA_02(x)            (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_SIPI_DATA_3 */

#define BIT_DMC_BIST_AUTO_BIST_SIPI_DATA_3_BIST_SIPI_DATA_03(x)            (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_SIPI_DATA_4 */

#define BIT_DMC_BIST_AUTO_BIST_SIPI_DATA_4_BIST_SIPI_DATA_04(x)            (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_SIPI_DATA_5 */

#define BIT_DMC_BIST_AUTO_BIST_SIPI_DATA_5_BIST_SIPI_DATA_05(x)            (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_SIPI_BIT_CTRL_0 */

#define BIT_DMC_BIST_AUTO_BIST_SIPI_BIT_CTRL_0_BIST_SIPI_BIT_PATTERN_0(x)  (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_SIPI_BIT_CTRL_1 */

#define BIT_DMC_BIST_AUTO_BIST_SIPI_BIT_CTRL_1_BIST_SIPI_BIT_PATTERN_1(x)  (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_0 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_0_BIST_DATA_00_PATTERN(x)         (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_1 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_1_BIST_DATA_01_PATTERN(x)         (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_2 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_2_BIST_DATA_02_PATTERN(x)         (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_3 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_3_BIST_DATA_03_PATTERN(x)         (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_4 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_4_BIST_DATA_04_PATTERN(x)         (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_5 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_5_BIST_DATA_05_PATTERN(x)         (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_6 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_6_BIST_DATA_06_PATTERN(x)         (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_7 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_7_BIST_DATA_07_PATTERN(x)         (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_8 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_8_BIST_DATA_08_PATTERN(x)         (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_9 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_9_BIST_DATA_09_PATTERN(x)         (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_10 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_10_BIST_DATA_10_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_11 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_11_BIST_DATA_11_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_12 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_12_BIST_DATA_12_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_13 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_13_BIST_DATA_13_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_14 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_14_BIST_DATA_14_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_15 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_15_BIST_DATA_15_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_16 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_16_BIST_DATA_16_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_17 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_17_BIST_DATA_17_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_18 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_18_BIST_DATA_18_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_19 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_19_BIST_DATA_19_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_20 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_20_BIST_DATA_20_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_21 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_21_BIST_DATA_21_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_22 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_22_BIST_DATA_22_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_23 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_23_BIST_DATA_23_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_24 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_24_BIST_DATA_24_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_25 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_25_BIST_DATA_25_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_26 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_26_BIST_DATA_26_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_27 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_27_BIST_DATA_27_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_28 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_28_BIST_DATA_28_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_29 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_29_BIST_DATA_29_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_30 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_30_BIST_DATA_30_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_USER_DATA_31 */

#define BIT_DMC_BIST_AUTO_BIST_USER_DATA_31_BIST_DATA_31_PATTERN(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_RESULT */

#define BIT_DMC_BIST_AUTO_BIST_RESULT_BIST_FINISH_FLAG                     BIT(1)
#define BIT_DMC_BIST_AUTO_BIST_RESULT_BIST_FAIL_FLAG                       BIT(0)

/* REG_DMC_BIST_AUTO_BIST_FAIL_ADDR */

#define BIT_DMC_BIST_AUTO_BIST_FAIL_ADDR_BIST_FAIL_ADDR(x)                 (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_FAIL_DATA_0 */

#define BIT_DMC_BIST_AUTO_BIST_FAIL_DATA_0_BIST_FAIL_DATA_0(x)             (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_FAIL_DATA_1 */

#define BIT_DMC_BIST_AUTO_BIST_FAIL_DATA_1_BIST_FAIL_DATA_1(x)             (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_FAIL_DATA_2 */

#define BIT_DMC_BIST_AUTO_BIST_FAIL_DATA_2_BIST_FAIL_DATA_2(x)             (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_FAIL_DATA_3 */

#define BIT_DMC_BIST_AUTO_BIST_FAIL_DATA_3_BIST_FAIL_DATA_3(x)             (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_LFSR_POLY */

#define BIT_DMC_BIST_AUTO_BIST_LFSR_POLY_BIST_LFSR_POLY_NEG(x)             (((x) & 0xFFFF) << 16)
#define BIT_DMC_BIST_AUTO_BIST_LFSR_POLY_BIST_LFSR_POLY_POS(x)             (((x) & 0xFFFF))

/* REG_DMC_BIST_AUTO_BIST_LFSR_SEED_0 */

#define BIT_DMC_BIST_AUTO_BIST_LFSR_SEED_0_BIST_DATA_LFSR_SEED_L0(x)       (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_LFSR_SEED_1 */

#define BIT_DMC_BIST_AUTO_BIST_LFSR_SEED_1_BIST_DATA_LFSR_SEED_L1(x)       (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_LFSR_SEED_2 */

#define BIT_DMC_BIST_AUTO_BIST_LFSR_SEED_2_BIST_DATA_LFSR_SEED_H0(x)       (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_LFSR_SEED_3 */

#define BIT_DMC_BIST_AUTO_BIST_LFSR_SEED_3_BIST_DATA_LFSR_SEED_H1(x)       (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_MISS_CNT */

#define BIT_DMC_BIST_AUTO_BIST_MISS_CNT_BIST_BWTEST_MISS_COUNTER(x)        (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_EXPT_DATA_0 */

#define BIT_DMC_BIST_AUTO_BIST_EXPT_DATA_0_BIST_EXPT_DATA_0(x)             (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_EXPT_DATA_1 */

#define BIT_DMC_BIST_AUTO_BIST_EXPT_DATA_1_BIST_EXPT_DATA_0(x)             (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_EXPT_DATA_2 */

#define BIT_DMC_BIST_AUTO_BIST_EXPT_DATA_2_BIST_EXPT_DATA_0(x)             (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_EXPT_DATA_3 */

#define BIT_DMC_BIST_AUTO_BIST_EXPT_DATA_3_BIST_EXPT_DATA_0(x)             (((x) & 0xFFFFFFFF))

/* REG_DMC_BIST_AUTO_BIST_XTK_MODE */

#define BIT_DMC_BIST_AUTO_BIST_XTK_MODE_BIST_XTK_RESV(x)                   (((x) & 0x7F) << 25)
#define BIT_DMC_BIST_AUTO_BIST_XTK_MODE_BIST_XTK_DBI_ON                    BIT(24)
#define BIT_DMC_BIST_AUTO_BIST_XTK_MODE_BIST_XTK_REPEAT_NUM(x)             (((x) & 0xFF) << 16)
#define BIT_DMC_BIST_AUTO_BIST_XTK_MODE_BIST_XTK_M_ED_VALUE(x)             (((x) & 0xFF) << 8)
#define BIT_DMC_BIST_AUTO_BIST_XTK_MODE_BIST_XTK_M_ST_VALUE(x)             (((x) & 0xFF))

/* REG_DMC_BIST_AUTO_BIST_FAIL_CNT */

#define BIT_DMC_BIST_AUTO_BIST_FAIL_CNT_BIST_DATA_FAIL_CNT(x)              (((x) & 0xFFFFFFFF))

#endif

